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STA Simulator
Safe Design
Setup Violation
Hold Violation
Sweep T
clk
(Test Fmax)
View: Both Paths
View: Setup Only
View: Hold Only
Parameters (ns)
Period (T
clk
)
10.0
Clk-to-Q (T
cq
)
1.0
Comb Max (T
c_max
)
6.0
Comb Min (T
c_min
)
2.0
Setup (T
su
)
1.0
Hold (T
h
)
1.0
Skew (T
skew
)
0.0
Uncertainty (T
unc
)
0.5
Max Frequency:
125
MHz
Interactive Timing Waveform
Delay Budget (Setup Path):
Setup Constraint Equation:
T
cq
+ T
c_max
+ T
su
+ T
unc
≤
T
clk
+ T
skew
Hold Constraint Equation:
T
cq
+ T
c_min
≥
T
h
+ T
skew
+ T
unc
Setup Analysis
Arrival:
7.0 ns
Required:
8.5 ns
Setup Slack (Req - Arr)
+1.5 ns
Hold Analysis
Arrival:
3.0 ns
Required:
1.5 ns
Hold Slack (Arr - Req)
+1.5 ns
Key Concepts
Setup Equation
T_clk ≥ T_cq + T_c_max + T_su − T_skew
Hold Equation
T_cq + T_c_min ≥ T_h + T_skew
Critical Path
The longest combinational delay path determines the maximum clock frequency.